`timescale 1ns/1ps

module testbench (
);

reg        clk       ;
reg        rst_n     ;
reg        rx        ;
wire        tx        ;
reg  [31:0] cnt       ;
reg  [7:0] data      ;
wire [23:0] led;
wire [7:0] seg_en;
wire seg_ca;
wire seg_cb;
wire seg_cc;
wire seg_cd;
wire seg_ce;
wire seg_cf;
wire seg_cg;
wire seg_dp;

wire rst = ~rst_n;

parameter baud_rate = 32'd230400;
parameter cycle_per_bit = 100000000/baud_rate;

initial begin
    clk   = 0;
    rst_n = 0;
    rx    = 1;
    cnt   = 0;
    data  = {1'b1, 7'd29};
    #20;
    rst_n = 1;
    #200000;
    $finish;
end

always #5 clk = ~clk;

always@(posedge clk) begin
    if (~rst_n) begin
        cnt <= 0;
    end
    else if (cnt == cycle_per_bit) begin
        cnt <= 0;
    end
    else begin
        cnt <= cnt + 1'b1;
    end
end

reg[3:0] data_cnt = 0;

always@(posedge clk) begin
    if (~rst_n) begin
        rx <= 1;
        data_cnt <= 0;
    end
    else if (cnt == cycle_per_bit) begin
        if (data_cnt == 0) begin
            rx <= 0;
            data_cnt <= data_cnt + 1;
        end
        else if (data_cnt <= 4'h8) begin
            rx <= data[data_cnt-1];
            data_cnt <= data_cnt + 1;
        end
        else begin
            data <= data-1;
            data_cnt <= 0;
            rx <= 1;
        end
    end
    else begin
        rx <= rx;
    end
end

top top (
    .clk    (clk       ),
	.rst    (rst       ),
	.rx     (rx        ),
	.tx     (tx        ),
	.led    (led),
	.seg_en (seg_en),
	.seg_ca (seg_ca),
	.seg_cb (seg_cb),
	.seg_cc (seg_cc),
	.seg_cd (seg_cd),
	.seg_ce (seg_ce),
	.seg_cf (seg_cf),
	.seg_cg (seg_cg),
	.seg_dp (seg_dp)
);

endmodule